1. Field of the Invention
The present invention relates to planarizing semiconductor devices in a Damascene process, and more particularly, to methods of planarizing a variety of surfaces of semiconductor devices by using first a diamond or a diamond-like carbon layer as a polish-stop layer, and then protecting such diamond-like carbon layer with a hard-mask, wherein such hard-mask may act as an additional polish-stop layer, thereafter chemically-mechanically polishing the surface of such semiconductor thereby producing an improved planarized surface.
2. Description of Related Art
Semiconductor devices can be patterned by a variety of methods, as disclosed in the prior art. A Damascene process flow is one such technique. Typically, a Damascene process comprises depositing an insulator material onto the surface of a substrate, patterning the insulator material to form openings for wires and vias, depositing a conductive material, generally a metal, into such openings and subsequently removing excess conductive material. Damascene processes may be used to form a variety of semiconductor surfaces, such as planarized multi-level metal interconnect structures, planarized shallow trench isolation structures, planarized semiconductor islands, and the like.
In patterning a semiconductor in a Damascene process, a substrate may be coated with a polymeric radiation-sensitive layer, known in the art as a resist layer. The resist layer is then developed. One such technique of developing a resist is to react the irradiated resist with an organometallic reagent and then subsequently expose the resist layer to an etchant, such as an oxygen plasma. Such an etchant removes the less etch-resistant, non-irradiated portions of the resist layer, thus layers applied to the substrate in a Damascene process, which are to be retained, must be resistant to such an etchant.
After formation of the patterned resist layer, the resist patterns are transferred into the substrate by an etch process. A conductive layer is then applied over the surface of the substrate, so that the conductive material fills the openings of the patterned substrate, contacting the device beneath. During the process of forming interconnect structures by a Damascene process, excess conductive material may accumulate at the surface of the semiconductor. Such excess conductive material may be removed by techniques such as chemical-mechanical polishing, thereby forming a substantially planar surface of the semiconductor device.
The use of chemical-mechanical polishing (CMP) processes to form flat planar surfaces of a semiconductor in a Damascene process are well established in the field. CMP processes enhance removal of non-planar regions of a surface by chemically reacting portions of the surface while mechanically applying force, thereby permitting a high degree of accuracy in the uniformity of polished semiconductor flatness. In a CMP process, it is desirable to consistently stop processing of a surface at a desired endpoint, thereby producing such a planar surface of the semiconductor. The use of polish-stop layers are well known in the art to stop a CMP process at such a desired endpoint. The prior art discloses a variety of methods of determining such endpoints. Generally, prior art discloses stopping polishing of a substrate at a desired endpoint in a CMP process by using techniques including, for example, copper as a polish-stop layer, time-to-polish stop layers, measuring thickness of the substrate, heat measurement stop-layers, and the like. However, the use of such polish-stop layers must be closely monitored otherwise over-polishing may occur, resulting in additional topography of the surface of the semiconductor.
CMP polish-stop layers are known in the art for use in global depositions processes, as well as in patterning a metal layer into an inter-level. As disclosed in the prior art, the use of polish-stop layers in Damascene processes may involve depositing a polish-stop layer over a planarized surface of the semiconductor and subsequently performing a CMP process. The CMP process in a Damascene process ends or stops at the polish-stop layer. Such disclosures teach the polish-stop layer may be deposited globally to the surface of the semiconductor or applied to fill apertures or openings in such surface.
In addition to global depositions in Damascene processes, polish-stop layers may be used in patterning a metal layer into an inter-level dieletric. In patterning a metal layer into an inter-level dielectric during a Damascene process flow, removal of the dielectric layer during a chemical-mechanical over-polish may create sufficient topography. This topography can consist of metal and dielectric surfaces that are at different heights, or can consist of dishing of both the metal and dielectric layers over relatively large areas. Thus a need exists to create an improved method of planarizing a substrate surface using a polish-stop layer with the ability to over-polish and create a substantially planarized surface.
The use of global disposition of diamond or a diamond-like carbon material as a polish-stop layer in a CMP process has been disclosed in U. S. Pat. No. 5,246,884 to Jaso et al, assigned to the present assignee. Jaso teaches the use of diamond or a diamond-like carbon material as a polish etch stop without patterning the semiconductor. However, no known art reports the use of diamond or a diamond-like carbon material as a polish-stop layer in patterning a metal layer into an inter-level dieletric in a Damascene process. The use of diamond or a diamond-like carbon material as disclosed in Jaso would not be effective as a polish-stop layer in a patterning step of a Damascene process, primarily due to the volatility of diamond or a diamond-like carbon material during such patterning step.
The present invention provides a method of patterning a metal layer into a multi-level dielectric in a Damascene process flow which significantly decreases the amount of topography created by the removal of the dielectric during the chemical-mechanical over-polish, wherein such method may be used to form a variety of semiconductor surfaces.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of forming a variety of planarized semiconductor surfaces in a Damascene process wherein there is a significant reduction in topography.
Another object of the present invention is to provide a method of reducing topography in the formation of a multi-level metal interconnect structure.
It is another object of the present invention to provide a method of reducing topography in the formation of a planarized semiconductor island.
A further object of the invention is to provide a method of reducing topography in the formation of a planarized shallow trench isolation structure.
It is another object of the present invention to provide a semiconductor structure having a polish-stop layer material wherein the thermal conductivity of the finished semiconductor chip is greatly improved.
Another object of the present invention is to provide a method of forming a planarized semiconductor with an improved ability to over-polish during the CMP process without creating additional topography.
It is another object of the present invention to provide a decrease in the amount of monitoring and control required for the processing of the chemical-mechanical polishing.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, method of planarizing a surface of a semiconductor in a Damascene process flow using diamond or a diamond-like material as a polish-stop layer comprising: optionally depositing a dielectric or conductive layer on the surface of a semiconductor, depositing a diamond or diamond-like layer on top of such dielectric or conductive layer, depositing a hard-mask layer which serves to protect the diamond or diamond-like layer during a patterning process, forming a plurality of openings, forming a metal layer, and then planarizing the surface of the semiconductor to form a substantially planarized surface.
In a preferred embodiment of the present invention discloses a method of planarizing a semiconductor by forming a first diamond-like carbon polish stop layer on a surface of a substrate, forming a second hard-mask layer on the surface of said first polish stop layer, wherein in addition to such second layer being a hard-mask, it further comprises a second polish stop layer, patterning the second layer to form a first set of openings, patterning an exposed portion of the first layer to form a second set of openings, and then patterning an exposed portion of the substrate to form a third set of openings. Thereafter, a third layer is formed on the surface of the substrate therein at least filling the third set of openings and subsequently the substrate surface is planarized to remove at least any excess of the third layer. The planarization may at least stop at the second hard-mask polish-stop to achieve an overall substantial planarity, or may continue to the diamond or diamond-like polish stop layer. The diamond or diamond-like polish stop layer allows for an over-polishing process while still maintaining a substantially planar surface of the substrate.
In a further aspect, the present invention describes a method of forming a planarized interconnect semiconductor structure in a Damascene process according to the method above.
In a further aspect, the present invention describes a method of forming a planarized semiconductor isolation structure in a Damascene process according to the method above.
In a further aspect, the present invention describes a method of forming a planarized semiconductor island structure in a Damascene process according to the method above.
Still another aspect of the invention is the disclosure of a semiconductor having a substantially planar surface formed by the method as described above.